Tanu Hari Dixit

Established in 1919, IIT BHU is one of the oldest higher education institutions in India and is widely regarded in terms of its influence, reputation, and academic pedigree.

During my time at IIT BHU, I learnt most of my key skills that have I have taken through my career such as teamwork and working to tight deadlines. I thoroughly enjoyed my time at university. I was awarded a silver medal for standing second position in Electronics Engineering, Class of 2017.

I spent a lot of my free time as a member of the Electronics Engineering Society and Fine Arts Club.

Working in the Security Platform Software team for delivering secure TI SoC's

I transitioned to being an Embedded Software Engineer in Embedded Processors group.

• Sitara Family of SoCs
  • Currently working on implementation of pre-silicon security firmware for a product in Sitara family of SoCs

Solving 21st century high speed communication problems by validating awesome products

I transitioned to being a Validation Engineer in High Speed Signal Conditioning group.

• High speed Cross Bar
  • Led the endeavour for delivering the comprehensive test program for a high priority customer.
• Low power Single channel USB2.0 to eUSB2.0 repeater:
  • Led the validation for the project and implemented methodologies and automation for the product.
• 4 channel 2:1 wideband high speed multiplexer:
  • Led the validation for the project
  • Implemented TRL Algorithm for accurate fixture removal for precision AC measurements (up till ~15GHz).
  • Automated and completed data collection and analysis of about ~50 devices (thereby busting myths of mass data collection for RF measurements)
• 2 channel 2:1 wideband high speed multiplexer:
  • Validated AC characteristics of the high speed switch (BW~12-13GHz).
  • Automated and analyzed data for AC characterization of the switch.

Solving 21st century high speed communication problems by designing blocks for awesome products

My role at Texas Instruments, was of Analog Design Engineer in High Speed Signal Conditioning group.

• 2 channel 2:1 high speed multiplexer:
  • Designed a low power DC-DC converter to provide overdrive scaling with common mode, to a high speed switch.
• USB 2.0 Redriver:
  • Designed a DC-DC converter (charge pump), Oscillator, and Power-on-reset circuit for a USB2.0 Redriver chip.
  • Wrote scripts in Python to help automate writing verilog-a for the digital design to smoothen analog design verification. Some of my scripts are still used in the flow.
• USB 2.0 Repeater:
  • Designed a DC-DC converter (charge pump), for a USB2.0-eUSB2.0 repeater , used in switches for HS mode USB2.0 communication.
  • Owned analog design verification for the project of various features.
• PLL 8G-11G Hz
  • Optimized the noise for the phase locked loop.
  • Designed the Charge Pump required for the PLL.
• PCIe retimer
  • Designed Reference clock input and output buffers.
  • Bug fixes to SMBUS 3.0 input and output buffers.
  • Owned verification of a PLL for reference clock.
  • Bug fixes to the verilog model for the PLL.

Led recitations and labs for Introduction to Computer Science, to students of Electronics Engineering’20 and Applied Physics’21.

Was part of a start up that makes highly personalized cards. The cards include a hand drawn sketch of the photograph sent to us and a poem written exclusively on the life story of the customer.

Designed a low noise DAC to remove the DC offset accumulated in direct-conversion receivers. Made heavy use of Cadence (Virtuoso) to simulate the design and tested INL, DNL, noise, output impedance and layout considerations.

Selected for the IASc-INSA-NASI Summer Research Fellowship, 2015, under the Indian Academy of Sciences. Worked as a Summer Research Fellow at Indian Institute of Technology, Kharagpur, India in summer, 2015 under the guidance of Dr. Debdeep Mukhopadhyay, in Secured Embedded Architecture Laboratory (​ SEAL​ ), Department of Computer Science. Implemented a Template power attack on a modular exponentiation algorithm called Joye’s Ladder for the public key cryptosystem, RSA. (used Xilinx Microblaze soft-core processor of SASEBO-W standard side-channel analysis board). Eventually, co-authored a research paper Template attack on SPA and FA resistant implementation of Montgomery Ladder got accepted in the IET (Institution of Engineering and Technology) Information Security special issue on Lightweight and Energy-Efficient Security Solutions for Mobile Computing Devices.

Gaussian Processes (GP) Regression and Classification for estimating Channel State Information
Worked under the guidance of Prof. K. V. Srinivas, Department of Electronics Engineering. The proposed algorithm tracks the states of the channels by using a learning algorithm and by judiciously probing a set of users whose channel states may have changed, for efficient allocation of limited and time-varying resources among multiple users to satisfy their requirements in wireless networks.

These are the ​ patches I contributed/bugs I identified ​ for ​ Sympy​ , a computer algebra system written in pure Python.